Generally, in a semiconductor circuit, various devices such as transistors, diodes, resistors and the like must be electrically isolated from each other. Because of the tendency toward high integration of semiconductor devices and because the channel length and the width of a field oxide layer for device isolation are reduced, micro patterns are needed to accomplish such isolation in device fabrication.
LOCOS (local oxidation of silicon) has been very popular as a device isolation method. The LOCOS method comprises: sequentially forming a pad oxide layer and a nitride layer on a silicon substrate; patterning the nitride layer; and forming a field oxide layer by selectively performing oxidation on the silicon substrate. One shortcoming of LOCOS device isolation is that a bird's beak often occurs at an edge of the field oxide layer because oxygen penetrates into a lateral side of the pad oxide layer from a bottom of the nitride layer used as a mask in the selective oxidation of the silicon substrate. The length of the bird's beak extends the field oxide layer to an active area, thereby shortening the channel length and increasing a threshold voltage to induce the so-called short channel effect. As a result, the electric characteristics of the transistor are degraded. Specifically, in a LOCOS device isolation exhibiting the short channel effect, the punch-through phenomenon takes place. Punch-through is a phenomenon which occurs when the channel length is reduced below 0.3 μm and the field oxide layers defining the active area merge into one. As a result, the field oxide layers are unable to secure an accurate width of the active area. Thus, certain limitations are placed on LOCOS device isolation.
Recently, trench isolation has been employed in semiconductor fabrication performed according to a design rule below 0.25 μm. Trench isolation comprises forming a trench by removing a portion of a semiconductor substrate and filling up the trench with an insulator.
In the latest device isolation techniques, shallow trench isolation is mainly used. Shallow trench isolation comprises: forming a trench by locally removing a portion of a silicon substrate; depositing an insulating layer, (e.g., an oxide layer), on the silicon substrate; and removing the insulating layer on an active area by CMP (chemical mechanical polishing) to leave only a portion of the insulating layer in the trench as a field isolation area. The STI method, which employs a trench depth below 3 μm, is applicable to a design rule below 0.15 μm.
The STI method reduces the size of the device isolation area relative to the substrate. In an STI method a trench provided in a semiconductor substrate is filled up with silicon oxide by CVD (chemical vapor deposition). The STI method prevents the bird's beak problem mentioned above to thereby avoid a loss of an active area that is planarized.
Meanwhile, as the gate length is decreased, the leakage current component occurring in the STI employing the trench device isolation layer is divided into diffusion current and a drift current. The drift current flows through a shortest distance between devices, but the diffusion current flows along an interface of the oxide layer.
As mentioned in the above explanation, the STI method comprises: forming a trench by etching a silicon substrate to a prescribed depth; depositing an insulating layer on the substrate and in the trench; and etching the insulating layer by an etch-back process or CMP to leave the insulating layer within the trench only. Currently, USG (undoped silicate glass), TEOS (tetraethyl orthosilicate), HTO (high temperature oxide), or a combination thereof is used as the oxide layer filling the trench. Such a filing material has a heat budget smaller than that of thermal oxide formed by oxidation, exhibits throughput higher than that of thermal oxide, and has a wet etch rate faster than that of thermal oxide.
A prior art semiconductor device isolation method using STI will now be explained with reference to FIGS. 1A to 1F. FIGS. 1A to 1F are cross-sectional illustrations of a prior art method of forming a trench type device isolation layer in a semiconductor device.
Referring to FIG. 1A, a pad oxide layer 13 is formed on a silicon substrate 11 by thermal oxidation.
A nitride layer 15 is deposited on the pad oxide layer 13.
Referring to FIG. 1B, a photoresist pattern 17 is formed on the nitride layer 15 to have an opening A that defines a device isolation area of the silicon substrate 11.
Referring to FIG. 1C, the nitride layer 15 and the pad oxide layer 13 are etched using the photoresist pattern 17 as an etch mask to expose a portion of the substrate 11.
The exposed portion of the substrate 11 is etched using the photoresist pattern 17 and the remaining nitride layer pattern 15′ and pad oxide layer pattern 13′ as a mask to form a trench B having a predetermined depth.
Optionally, after the photoresist pattern 17 has been removed, the trench B may be formed using the remaining nitride layer pattern 15′ and pad oxide layer pattern 13′ as an etch mask.
The trench B is formed for shallow trench isolation.
Referring to FIG. 1D, after the photoresist pattern 17 has been removed; a liner oxide layer 19 is formed on an inside of the trench by STI liner oxidation to prevent STI damage. The liner oxide layer 19 is used to solve the problems of stress generated from the expansion of a filled oxide layer that will be formed later by oxidation. Specifically, the liner oxide layer 19 functions as an oxidation barrier suppressing oxidant diffusion into the sidewalls of the trench.
Referring to FIG. 1E, a gap-fill material layer 21 such as a TEOS (tetraethyl orthosilicate) layer or a HDP (high density plasma) CVD layer is deposited over the substrate 11 including the liner oxide layer 19 thereby filling the trench.
Referring to FIG. 1F, the gap-fill material layer 21 is planarized by chemical mechanical polishing (CMP) to expose the nitride layer pattern 15′.
Annealing is then performed on the substrate at a prescribed temperature.
Subsequently, the pad oxide layer pattern and the nitride layer pattern are removed by wet etching.
The gap-fill material layer 21 in FIG. 1E remains in the trench and, thus, becomes an STI layer 21′.
A method of forming a trench device isolation layer of a semiconductor device is described in Korean Patent Application No. 1999-45566, filed on Oct. 20, 1999. This method employs a SiN liner oxide layer formed by low pressure CVD.
Specifically, the method described in Korean Patent Application No. 1999-45566 comprises: forming a trench on a field area of a semiconductor substrate; growing a thermal oxide layer on an inside of the trench; forming a silicon oxy nitride (SiON) layer on an interface between the thermal oxide layer and the silicon substrate by annealing in an ambience of N2O; forming an oxidation barrier layer by depositing silicon nitride on an inside of the trench; filling the trench with an oxide layer; and planarizing the oxide layer to form a device isolation layer. This method forms a device isolation layer capable of preventing out-diffusion of boron (B) with less stress.
However, as the width of the trench is decreased due to a reduced design rule or scale, the process/device margin is shortened. The conventional STI is unable to control leakage current and diffusion current despite the excellent device isolation feature.
Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like parts.